1. Technical Field
Exemplary embodiments of the present invention relate to circuits, and more particularly, to circuits and methods for generating a common voltage.
2. Discussion of the Related Art
Various types of flat panel displays, such as a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescence display panel, etc., have been developed to replace conventional cathode ray tube (CRT) displays. Such flat panel displays are suitable for devices and applications requiring small size, light weight and low power consumption. For example, the LCD can be driven by large scale integration (LSI) drivers since the LCD can be operated at a low-power supply voltage and thus has low power consumption. Therefore, the LCD has been widely implemented for laptop computers, cellular phones, pocket computers, automobiles, color televisions, etc. Such characteristics of LCDs as the small size, light weight and low power consumption render LCDs suitable for use with portable devices.
FIG. 1 is a diagram illustrating a conventional display system.
Referring to FIG. 1, a display system 100 includes a display panel 110 (e.g., an LCD) and a plurality of components for driving and controlling the display panel 110. The plurality of components include a source driving integrated circuit (IC) 120, a gate driving IC 130, a controller 140 having graphic random access memory (GRAM), and a power generator 150. The controller 140 generates control signals to control the power generator 150, the source driving IC 120, and the gate driving IC 130.
The display panel 110 is coupled to the source driving IC 120 through a plurality of data lines D1 through Dm and coupled to the gate driving IC 130 through a plurality of gate lines G1 through Gn. The display panel 110 includes a plurality of pixels/subpixels that are arranged in a matrix of rows and columns. The pixels/subpixels in a given row are commonly coupled to a gate line and the pixels/subpixels in a given column are commonly coupled to a data line. Depending on the design of the display panel 110, one pixel/subpixel may be formed at each intersection of a gate line and a data line.
If the display panel 110 is a thin-film transistor (TFT) LCD, the display panel 110 includes a TFT board comprising a plurality of pixels/subpixels arranged in matrix form. As shown in FIG. 1, each pixel/subpixel unit includes a TFT, a liquid crystal capacitor CL, which is connected between a drain electrode of the TFT and a common electrode VCOM, and a storage capacitor Cst, which is connected in parallel with the liquid crystal capacitor CL. The storage capacitor Cst stores an electric charge and an image on the display is maintained during a non-selected period. The liquid crystal capacitor CL is formed by a common electrode VCOM of a plate, a pixel electrode of the TFT and liquid crystal material therebetween. A source electrode of the TFT is coupled to a data line, and a gate electrode of the TFT is coupled to a gate line. The TFT acts as a switch that applies a source voltage on the data line to the pixel electrode when a gate driver signal VGH on the gate line is applied to the gate of the TFT.
The power generator 150 generates a plurality of reference voltages, including a source driver power supply AVDD and a gamma reference voltage GVDD that are applied to the source driving IC 120. A high common electrode voltage VCOMH and a low common electrode voltage VCOML are applied to the common electrode VCOM of the display panel 110. A gate driver turn-on voltage VGON and a gate driver turn-off voltage VGOFF are applied to the gate driving IC 130 and selected gate lines are driven.
The controller 140 receives as input a plurality of driving data signals and driving control signals that are output from an image supply source (e.g., a main board of a computer). The driving data signals include red-green-blue (RGB) data for forming an image on the display panel 110. The driving control signals include vertical synchronous signals (Vsync), horizontal synchronous signals (Hsync), a data enable signal (DE) and a clock signal (CK). The controller 140 outputs to the source driving IC 120 a plurality of display data signals DDATA which correspond to RGB data and source control signals. The controller 140 outputs gate control signals to control the gate driving IC 130. The controller 140 controls the timing at which data and control signals are output from the source driving IC 120 and the gate driving IC 130. For example, in one mode of operation, the controller 140 generates the source and gate control signals such that the gate driving IC 130 transmits a gate driver output signal VGON to each of the gate lines G1 through Gn in a consecutive manner, and a data voltage is selectively applied one-by-one to each pixel/subpixel in an activated row, in order. In another mode of operation, the pixels/subpixels can be charged by sequentially scanning pixels/subpixels in a first column and thereafter scanning pixels/subpixels in a next column.
The gate driving IC 130 includes a plurality of gate drivers that respectively drive the corresponding gate lines G1 through Gn. The source driving IC 120 includes a plurality of source driver circuits 120-1 through 120-m which respectively drive the corresponding data lines D1 through Dm.
FIG. 2 is a diagram illustrating a conventional common voltage generating circuit that is included in the power generator in FIG. 1.
Referring to FIG. 2, a conventional common voltage generating circuit 200 includes an input reference voltage generator 210, a first operational amplifier (op-amp) 222, a second op-amp 224, a third op-amp 226, and a fourth op-amp 228.
The input reference voltage generator 210 receives a value of a first register VCMH[n:1] that is set to a target value of a maximum voltage of a common voltage, and a value of a second register VCMA[m:1] that is set to a target value of an amplitude of the common voltage. Thus, the input reference voltage generator 210 outputs a maximum input reference voltage VCMH_R and an amplitude input reference voltage VCMA_R.
When an input offset voltage of the op-amps 222, 224, 226, and 228 is “0,” a voltage at a node N1 is (a+1)VCMH_R. When a gain of the second op-amp 224 is “1,” a voltage at a node N2 is (a+1)VCMH_R. When the gain of the third op-amp 226 is “1,” a voltage at a node N4 is VCMA_R. A voltage at a node N3 is (a+1)/(b+1)×VCMH_R and a voltage at a node N5 is (a+1)/(b+1)×VCMH_R. Therefore, a voltage at a node N6 is (a+1)VCMH_R−b×VCMA_R. Namely, VCOMH, the voltage of the node N2, is (a+1)VCMH_R, and VCOML, the voltage of the node N6, is (a+1)VCMH_R−b×VCMA_R. Accordingly, VCOML is VCOMH−b×VCMA_R.
However, a practical op-amp has an input offset voltage due to mismatches, etc. When the input offset voltage of each of the op-amps 222, 224, 226, and 228 is Voff1, Voff2, Voff3, and Voff4, respectively, VCOMH and VCOML are determined by Equation 1 and Equation 2:VCOMH=(a+1)VCMH—R−((a+1)Voff1+Voff2)  Equation 1VCOML=VCOMH−b(VCMA—R)−((a+1)Voff1+Voff2+bVoff3+(b+1)Voff4)  Equation 2
(a+1)Voff1+Voff2, the offset voltage generated at the output of VCOMH, is cumulatively represented at the output of VCOML. Resistances bR2 and R2 dividing VCOMH are used for calculating VCOML. The resistances bR2 and R2 have high values and the generating current is decreased. Because sizes of the resistances bR2 and R2 increase, when considering a whole chip, a problem of block size appears. In addition, when VCOMH is applied to the op-amp 228 calculating VCOML, noise and overcurrent may be generated by peak noise that is generated when driving VCOM. Thus, a problem of requiring an output terminal buffer 224 appears. Because VCOML is calculated from VCOMH, the conventional common voltage generating circuit may have problems of size and accumulation at VCOML of an offset voltage that is generated at VCOMH.